1. Field of the Invention
This invention relates generally to frequency synthesizers and more particularly to such a synthesizer which is capable of fast switching times, good noise suppression, and extremely high resolution in frequency.
2. Cross Reference to Related Applications
The inventor's application (Ser. No. 07/769,093 Rational Fraction Synthesizer), submitted on Sep. 30, 1991, and the inventor's U.S. Pat. No. 5,144,254 dated Sep. 1, 1992, are incorporated herein by reference.
3. Description of the Prior Art
The frequency synthesizer is a well known and widely used electronic subsystem. Basically, frequency synthesis involves two distinct approaches, sometimes referred to as direct synthesis and indirect synthesis. All such synthesizers utilize a source of reference frequency, such as a quartz oscillator, or atomic standard, or some other highly accurate, fixed frequency reference. The source frequency itself is then operated on to provide a wide band of frequencies, each possessing the stability or accuracy of the source. In the direct synthesis approach, the designer may employ dividers, multipliers and such devices which operate on the frequency standard to derive the required output range of frequencies.
In the indirect approach, a VCO or controllable oscillator or other tunable source is used as a generator of the frequency range desired and this is then locked to the source by means of a frequency locked or phase locked loop. Thus one need not utilize complicated filtering schemes as necessary in the direct synthesis approach.
While the frequency synthesizer is characterized above as a separate test instrument, the techniques have found widespread use in the communications field as a local oscillator for a radio receiver or transmitter. A good description of some representative synthesizer techniques appear in books such as Digital PLL Frequency Synthesizers by Ulrich L. Rohde (1983); Frequency Synthesizers; Theory and Design 3.sup.rd Ed. by Vadim Manassewitsch; and Microwave Frequency Synthesizers by Ronald C. Sterling.
A commonly used prior art frequency synthesizer is the conventional divide-by-N phase locked loop (PLL) design that generates frequencies which are multiplers of a comparison frequency. More specifically, such a frequency synthesizer consists of a voltage (or current) controlled oscillator (VCO), divide-by-N logic which divides the output frequency of the VCO by N to produce a signal of frequency F.sub.C, and a phase (and/or frequency) detector which receives the divided signal at one input thereof and the reference frequency signal of frequency F.sub.ref at the other input thereof. The output of the phase detector is supplied back to the frequency control input of the VCO through a loop filter so that the output frequency of the VCO, after being divided by N, is equal to the frequency of the reference signal. By changing the value of N, F.sub.out can be changed in frequency steps equal to F.sub.ref.
The prior art also includes the ability to divide a reference signal by M before it is input to the phase detector at a comparison frequency F.sub.C. This is done because the best frequencies for building good reference clocks (e.g.: 3 to 5 MHz for crystals) are often not the desired frequencies for comparison F.sub.C. Thus an M divider is often used to divide down from the best F.sub.ref frequency to the chosen F.sub.C ; but the divider is fixed at one value--or occasionally two, when two different F.sub.C 's are to be provided. Thus even if the prior art apparatus allowed M to be programmed, said programming was done just once, and not updated for each new requested F.sub.out. To improve the frequency resolution of such prior art synthesizers, the designer must decrease F.sub.C, but many important characteristics such as speed of lock, noise rejection (especially microphonics), F.sub.C rejection, and so on limit the amount by which F.sub.C can be reduced. A similar tradeoff exists even in the present invention, but the teaching of this invention makes the tradeoff much less strict.
Other prior art combines a single PLL and a variable timebase. This combination may take any of several forms. First, a single PLL may be driven by a direct digital synthesizer (DDS) subsystem used as a variable timebase, wherein the PLL becomes a "course" loop, while the DDS forms a "fine" source. The DDS is called on to "fill in the steps" between the "course" steps of the PLL. Such art has become more popular, but it still is expensive and still has inherent noise problems. Another version uses a PLL driven by a variable clock consisting of a crystal oscillator that is "pulled" by a small amount, again to effectively fill in between the "course" steps of the final loop. Though this latter technique is less expensive and does not have the noise problems of the DDS technique, it does have at least three problems of its own: First, the output is now based not on a high quality stable source, but rather on a "pulled" crystal, so overall accuracy and stability are compromised. Second, an "external timebase in" cannot be used, because the "pulled" crystal is not locked to anything. Third, an "internal timebase out" cannot be provided, because none exists; the "pulled" crystal signal is of little value to a user, because it is not constant or at a "standard" frequency. And even if a user just used it relative to the overall synthesizers output, said overall output would then fall back to only having "course" resolution relative to the (variable) timebase out.
Another characteristic of prior art variable clocks, is that they must be designed to have their step size approximately constant, whereby the gaps between the "course" steps can be filled in evenly. The "steps" of the present inventions adjustable timebase are not required to be even, as will be described below.
Synthesizers that use two phase-locked loops responsive to the same reference signal, and where the outputs of the two PLL's are combined to form F.sub.out (typically using a mixer and filters, to effectively "add" or "subtract" the two frequencies), are known in the art. Such synthesizers where the combined signal is instead used in the feedback path of one of the PLL's, are also known in the art. The prior art, however, does not generally program all four of the division numbers, nor re-program all four for each new requested frequency. Nor does this prior art have a calculation means with a calculation procedure for finding the best integer values for the programmable divisions. Also, the final resolution of such prior art combined PLL schemes, is typically that of one of the PLL's. Said prior art would often identify one loop as "course" and the other as "fine", but would again end up with the overall resolution equal to the comparison frequency F.sub.C of one of the loops (the "fine").
Other prior art (this inventors application Ser. No. 07/769,093, entitled "Rational Fraction Synthesizer") teaches a synthesizer wherein the final resolution is better--often much better--than F.sub.C, and one could imagine two such prior art synthesizers having their outputs combined through addition and subtraction. Though several advantages might accrue from such a combination, its final resolution would still only be that of the better of the two. The present invention, by calculating division numbers for both PLL's at the same time, can provide a synthesizer that synergistically combines the calculations for the two PLL's, and wherein the combined resolution is considerably better than the resolution of either PLL separately.
Further prior art (this inventors U.S. Pat. No. 5,144,254 entitled "Dual Synthesizer") teaches the use of two PLLs, connected essentially in series, and a method for producing F.sub.out therewith. Said art can, in its dual-factor embodiment, approach frequency resolution similar to that provided by the present invention, but only under the condition that the former can, for each F.sub.req, successfully factor two different numbers (Y.sub.i and X.sub.i), versus the present inventions considerably relaxed requirement that it be able to successfully factor only one number (Y.sub.i).